This invention relates to a digital computer of the type executing instructions in a pipeline mode.
In a digital computer of the type which is capable of above described, each of a plurality of instructions is divided into a plurality of stages, and different stages of different instructions are executed in parallel, so that the plural instructions can be executed substantially in parallel relation.
However, when data required for processing according to an instruction B is obtained utilizing the result of operation specified by a preceding instruction A, execution of the instruction B must be deferred until the result of operation specified by the instruction A is established. Such a situation occurs in, for example, the case in which the contents of a base register or an index register are updated or renewed as a result of execution of the instruction A, and the new contents of the base register or index register are added to the address information included in the instruction B by execution of the instruction B so as to calculate the absolute address for access to a main memory. Thus, under such a situation, the result of operation according to the instruction A must be used for the execution of the instruction B. Occurrence of such a situation will be called hereinafter the presence of an address conflict. In such a case, execution of the address calculation stage of the instruction B is deferred until the operation of the instruction A is completed.
In order to minimize this delay, a secondary execution unit which can execute only simple operations required by part of the instructions has hitherto been provided separately from a primary execution unit which can execute operations required by all of the instructions. Such a secondary execution unit of relatively simple construction is generally disposed near the general register including the base register or the index register, and the primary execution unit of complex construction, hence, of larger circuit scale is disposed remote from the general register relative to the secondary execution unit. Operations that can be executed by either of the primary execution unit and secondary execution unit are executed by both of these execution units. When, for example, the instruction A above described requires an operation using only the data stored in the general register, this operation is executed by both of the primary execution unit and the secondary execution unit. When the primary execution unit and the secondary execution unit are simultaneously actuated or placed in operation, the operand required for the operation is supplied to the secondary execution unit earlier than the primary execution unit, and, therefore, the secondary execution unit generates the result of operation earlier than the primary execution unit, due to the fact that the secondary execution unit is disposed nearer to the general register than the primary execution unit. Therefore, by using the output from the secondary execution unit for the address calculation of the instruction B, the address calculation of the instruction B can be started earlier than when the output from the primary execution unit is used for the calculation. In this manner, an undesirable delay of the address calculation of the instruction B due to the address conflict can be minimized. Thus, the secondary execution unit functions to obviate the address conflict situation as early as possible so as to ensure data processing at a high speed.
The same problem occurs also when a branch-on-condition instruction is to be executed. In the execution cycle of the branch-on-condition instruction (which will be abbreviated hereinafter as a BC instruction), a condition code determined before the execution cycle is used to judge whether or not the branch is sucessful. Therefore, when an instruction D preceding this BC instruction instructs an operation which changes the condition code, the branch judgment cannot be made until the operation according to the preceding instruction D is completed. In such a situation, the branch judgment for the BC instruction must be made after the end of operation according to the preceding instruction D. Occurrence of such a situation is called hereinafter the presence of a condition code conflict. According to the prior art, the condition code determined by the secondary execution unit is used to judge whether or not the branch is successful so as to expedite the branch judgment.
However, data processing at higher speeds is now increasingly demanded.